Espressif Systems /ESP32-P4 /SPI1 /SPI_MEM_FLASH_WAITI_CTRL

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Interpret as SPI_MEM_FLASH_WAITI_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_MEM_WAITI_EN)SPI_MEM_WAITI_EN 0 (SPI_MEM_WAITI_DUMMY)SPI_MEM_WAITI_DUMMY 0 (SPI_MEM_WAITI_ADDR_EN)SPI_MEM_WAITI_ADDR_EN 0SPI_MEM_WAITI_ADDR_CYCLELEN 0 (SPI_MEM_WAITI_CMD_2B)SPI_MEM_WAITI_CMD_2B 0SPI_MEM_WAITI_DUMMY_CYCLELEN 0SPI_MEM_WAITI_CMD

Description

SPI1 wait idle control register

Fields

SPI_MEM_WAITI_EN

1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.

SPI_MEM_WAITI_DUMMY

The dummy phase enable when wait flash idle (RDSR)

SPI_MEM_WAITI_ADDR_EN

1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.

SPI_MEM_WAITI_ADDR_CYCLELEN

When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.

SPI_MEM_WAITI_CMD_2B

1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.

SPI_MEM_WAITI_DUMMY_CYCLELEN

The dummy cycle length when wait flash idle(RDSR).

SPI_MEM_WAITI_CMD

The command value to wait flash idle(RDSR).

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